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Omarmuhammadmu / FFE_digital_implementation

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The implementation of a FFE using only one adder and one multiplier. Specifications include a 1 MHz input data frequency and a 4 MHz FFE clock frequency, with the output being a 12-bit signed value available every 4 FFE clock cycles. The paper details the design, provides pseudo code, Verilog code, the Verilog netlist, and suggests optimizations.

electronics rtl verilog digital-design ffe cairo-university feed-forward-equalizer
  • Updated Jun 18, 2024
  • Verilog

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