fifo-buffer

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

RingBuffer (FIFO) for C (e.g. for STM32)

Implementation of a circular queue in hardware using verilog.

StreamBuffer is a single-class Java library that bridges an OutputStream and an InputStream through a dynamic, unbounded FIFO queue — solving the fixed-buffer and potential deadlock limitations of Java's built-in PipedInputStream/PipedOutputStream.

A ring buffer (FIFO) library for C and C++

Simple and lightweight FIFO\LIFO buffer library for the Arduino.

In this project, I investigate and design a NoC system consisting of the router/switch, IPs (CPU or other hardware module), and interconnection structure (topology) such as Mesh.

FSM based SPI/SSP Master and Slave Verilog Module

Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL

FIFO Buffer Implemented in VHDL

Advanced UART core on Spartan-3E FPGA using Verilog, featuring FSM-based TX/RX logic, FIFO buffering, and configurable baud rate generation, built and tested on Ubuntu Linux using Xilinx ISE.

A Synchronous FIFO Implementation for FPGA-Based Systems

Designed an Asynchronous FIFO based on Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons

Designed a synchronous FIFO inspired by the paper Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons

Library for the PTSolns I2Connect ICP-20100 barometric pressure and temperature module. Provides a streamlined interface to read high-accuracy barometric pressure and temperature data, utilize onboard FIFO buffers, and configure hardware interrupts for the ICP-20100 sensor using I2C.

Repo containing implemented FPGA projects