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chiselverify / chiselverify

A dynamic verification library for Chisel.

testing coverage scala verification chisel constrained-random-verification functional-coverage bus-functional-model chisel-test timed-assertions

Updated Nov 9, 2024
Scala

fvutils / pyvsc

Star

Python packages providing a library for Verification Stimulus and Coverage

python coverage randomization constraints constrained-random cocotb verification-stimulus random-stimulus functional-coverage

Updated Aug 31, 2026
Python

tmeissner / psl_with_ghdl

Star

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Feb 16, 2026
VHDL

fvutils / pyucis

Star

Python API to Unified Coverage Interoperability Standard (UCIS) Data

functional-coverage ucis accellera-ucis coverage-database

Updated Aug 31, 2026
Python

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

Star

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design

Updated Jun 26, 2024
Verilog

Yashas2801 / UART-Verification-using-UVM

Star

UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.

functional-coverage uart-verification uvm-testbench wishbone-interface

Updated Feb 26, 2025
Verilog

wendigp / Development-of-AXI4-Verification-IP-VIP-using-UVM

Star

Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.

protocol randomization vip scoreboard systemverilog questasim uvm axi amba sva axi4 functional-coverage uvm-verification constrained-randomization asserti

Updated Mar 7, 2026
SystemVerilog

gopro-uvm-rtl-verification / RISC-V-CPU-Core-UVM-Based-ISA-Compliance-Verification

Star

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

python jenkins cpu processor verification dpi spike riscv isa vcs systemverilog uvm constrained-random sva rv32im questa functional-coverage

Updated Aug 20, 2025
SystemVerilog

Vivek-Dave / UVM_TestBench_For_S_R_Latch

Star

Simple and Complete UVM TestBench For Verification Of S R Latch

verification uvm functional-coverage

Updated Jun 19, 2021
SystemVerilog

TatsuProject / rvgen

Star

Pure-Python RISC-V instruction generator with built-in functional coverage, auto-regression, and CI-ready dashboards.

python verification riscv risc-v cgf random-testing hardware-verification functional-coverage instruction-generator coverage-driven

Updated Jun 14, 2026
Python

gopro-uvm-rtl-verification / Async-Fifo-Cdc-Uvm-Verification

Star

UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

makefile verification vcs systemverilog fifo cdc uvm testbench sva metastability functional-coverage async-fifo questa-sim

Updated Aug 22, 2025
SystemVerilog

Tharunreddym / riscv-pipeline-verification

Star

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

c-plus-plus verification verilog scoreboard regression-testing systemverilog uvm constrained-random risc-v asic-verification questa dpi-c functional-coverage rtl-verification pipeline-verification

Updated May 19, 2026
SystemVerilog

abdo-ehab-euv / sram-controller-uvm-verification

Star

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project

Updated May 14, 2026
SystemVerilog

wendigp / AHB_APB_Bridge_Verification

Star

UVM-based verification of an AHB-to-APB bridge, validating protocol compliance, address decoding, data integrity, error handling, and corner cases using constrained-random testing and functional coverage.

randomization bridge verilog scoreboard systemverilog protocols uvm amba apb ahb functional-coverage constrainted-randomization

Updated Jul 12, 2025
SystemVerilog

harishchittaragi / DVFT11

Star

Hands-on Design Verification — SystemVerilog testbenches, full UVM environment for APB Protocol, Python scripting, SVA assertions & functional coverage. Trained at ChipEdge using Synopsys VCS.

python-script verilog synopsis systemverilog sva design-verification functional-coverage uvm-testbench apb-protocol

Updated Jul 23, 2026
SystemVerilog

ScottyB55 / I2C_Chip_Verification

Star

UVM verification environment for an I2C controller (constrained-random + assertions + functional coverage) — Questa/ModelSim

asic i2c verification systemverilog modelsim uvm sva questa functional-coverage

Updated Jan 9, 2026
VHDL

iceTo1 / sv-pipelined-cpu-uvm

Star

Custom 16-bit 3-stage pipelined CPU in SystemVerilog with UVM verification, RAW hazard handling, assertions, constrained-random testing, and functional coverage.

cpu pipeline verification assertions rtl systemverilog uvm constrained-random-verification functional-coverage uvm-verification cadence-xcelium uvm-testbench

Updated Aug 22, 2026
SystemVerilog

Vivek-Dave / UVM_TestBench_For_Ring_Counter

Star

Complete UVM TestBench For Verification Of Ring (Onehot) Counter

uvm functional-coverage

Updated Jun 19, 2021
SystemVerilog

jayabhiram / AHB_APB_Bridge

Star

AHB to APB Bridge Design and UVM-based Verification as per AMBA specifications.

verilog systemverilog vlsi vlsi-design functional-coverage uvm-verification digitalelectronics

Updated Feb 20, 2026
JavaScript

YeeDEA / mac-array-dv

Star

A 4x4 INT8 output-stationary MAC array in SystemVerilog, verified with a from-scratch UVM 1.2 environment - constrained-random stimulus, reference-model scoreboard, SVA, functional coverage, and Python-driven regression.

fpga verification rtl vivado systemverilog uvm sva design-verification functional-coverage hardware-design

Updated Aug 14, 2026
Python

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functional-coverage

Here are 56 public repositories matching this topic...

chiselverify / chiselverify

fvutils / pyvsc

tmeissner / psl_with_ghdl

fvutils / pyucis

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

Yashas2801 / UART-Verification-using-UVM

wendigp / Development-of-AXI4-Verification-IP-VIP-using-UVM

gopro-uvm-rtl-verification / RISC-V-CPU-Core-UVM-Based-ISA-Compliance-Verification

Vivek-Dave / UVM_TestBench_For_S_R_Latch

TatsuProject / rvgen

gopro-uvm-rtl-verification / Async-Fifo-Cdc-Uvm-Verification

Tharunreddym / riscv-pipeline-verification

abdo-ehab-euv / sram-controller-uvm-verification

wendigp / AHB_APB_Bridge_Verification

harishchittaragi / DVFT11

ScottyB55 / I2C_Chip_Verification

iceTo1 / sv-pipelined-cpu-uvm

Vivek-Dave / UVM_TestBench_For_Ring_Counter

jayabhiram / AHB_APB_Bridge

YeeDEA / mac-array-dv

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